1. Field of the Invention
This invention relates in general to a process for fabricating bitlines for semiconductor DRAM devices and, in particular, to a process for fabricating bitlines for DRAM devices having reduced contact resistance and improved reliability.
2. Description of Related Art
A typical fabrication process for DRAM devices is the so-called 4P2M process that incorporates four layers of polysilicon and two layers of metal interconnections. The first of the four polysilicon layers employed, as viewed from the bottom of the substrate, is the polysilicon layer for the transistor gate electrode. The second layer is the polysilicon for the bottom electrode of the storage capacitor of the memory cell unit. The third is the polysilicon for the top electrode of the storage capacitor, and the fourth is the one for bitlines. On the other hand, the two layers of metal interconnections are used to connect all the circuitry configurations embedded in the substrate, including the four polysilicon layers.
For the fabrication of the bitlines in typical DRAM devices, polycide made from the composition of doped polysilicon and tungsten silicide (WSi.sub.x) is frequently used to form the electrical conductor paths in the device. In forming this polycide, tungsten silicide is normally obtained in a deposition procedure employing a gas supply containing tungsten hexafluoride that is used in chemical reaction with silane (SiH.sub.4).
As a material for the contact plugs for DRAM bitlines, tungsten silicide is advantageous in that the phenomenon of static charge capacitance can be reduced in order to improve the device operating speed. However, tungsten silicide has a principle drawback when used to fabricate contact plugs for bitlines. Tungsten silicide is characterized by its relatively poor step coverage when deposited. Therefore, when there is large aspect ratio arising in the structural configuration of the device substrate, tungsten silicide is less capable of achieving good contact with the fourth polysilicon layer of the DRAM device. Total coverage by tungsten silicide is, in general, very difficult to achieve.
In order to solve this problem, di-chloro-silane (DCS) was proposed to replace silane that was used to react with the tungsten hexafluoride-containing gas in the chemical vapor deposition (CVD) procedure used to deposit tungsten silicide. Although step coverage was indeed improved, however, when the step height in the contact opening formed in the structural configuration is in exceed of about 10 k.ANG., there are still the unacceptable step coverage conditions encountered, in particular, in the contact openings for the bitlines.
FIGS. 1A.about.1D respectively are cross-sectional views of a DRAM device fabricated in a conventional process. In the cross-sectional view of FIG. 1A, a MOS transistor and its corresponding storage capacitor for a memory cell unit of the DRAM device being fabricated has already been formed over the surface of the substrate 10. As illustrated, the MOS transistor of the entire system of the DRAM device includes the source/drain regions 9, the field oxide layer 11, a first polysilicon layer 12, sidewall spacer 13, and a first oxide layer 17. The first polysilicon layer 12 may be a stacked structure including a doped polysilicon layer 16, a tungsten silicide layer 15, and a silicon nitride layer 14 subsequently stack in that order. The first oxide layer 17 is typically formed in a low-pressure CVD (LPCVD) procedure conducted to deposit a tetraethoxysilane (TEOS) oxide. The deposited TEOS oxide layer covers the field oxide layer 11, the first polysilicon layer 12, as well as the sidewall spacer 13. A photolithography procedure is then employed to pattern into the TEOS oxide layer to form the oxide layer 17. Designated areas of the substrate 10 where the source/drain regions 9 of the MOS transistor located are exposed out of the coverage of this oxide layer 17.
The storage capacitor includes a bottom electrode consisting of the second polysilicon layer 18 covered by a hemispherical-grain polysilicon (HSG-Si) layer 19. On top of the bottom electrode is a dielectric structure 20 consisting of a three-layered oxide-nitride-oxide (ONO) configuration in which the oxide may be tantalum oxide (Ta.sub.2 O.sub.5) and the nitride may be titanium nitride (TiN). The third polysilicon layer 21 constitutes the top electrode for the storage capacitor of the memory cell unit.
Then, as is illustrated in FIG. 1B, a second oxide layer 22 and a borophosilicate glass (BPSG) layer 23 may be deposited subsequently over the surface of the third polysilicon layer 21. The second oxide layer 22 may be deposited, for example, in an atmospheric pressure CVD (APCVD) procedure.
With reference to FIG. IC, a photolithographic procedure is then employed to pattern the BPSG layer 23, the first oxide layer 17 and the second oxide layer 22. The result is the formation of the contact openings 24 for the bitlines which reveal the transistor source/drain regions 9 over the surface of the device substrate 10.
Next, with reference to FIG. 1D, the fourth polysilicon layer 25 is deposited to a thickness of about 1 k.ANG.. This fourth polysilicon layer covers the BPSG layer 23, as well as fills into the contact openings 24. The fourth polysilicon layer 25 is then subject to an ion implantation procedure that improves electrical conductivity in it. Afterwards, a tungsten silicide layer 26 is deposited to cover the fourth polysilicon layer 25. The tungsten silicide layer 26 may be deposited in an LPCVD procedure employing a reaction gas containing tungsten hexafluoride. This reaction gas is then mixed with silane at a temperature of about 300.about.400.degree. C. to incur chemical reaction so that tungsten silicide can be deposited to form layer 26. The fourth polysilicon layer 25 and the tungsten silicide layer 26 are then patterned to form bitlines for the memory cell units.
During the process of the formation of tungsten silicide layer 26, it is found that it is difficult for tungsten silicide to fill completely into the contact openings 24. Imperfect filling in the openings 24 results in the increase of contact resistance between the bit lines behind the plug formed in the openings 24 and the transistor source/drain regions 9 underneath. Further, due to the fact that tungsten silicide exhibits high coefficient of reflection, necking or V-notching phenomena are observed when photoresist layer is applied over its surface when a procedure of photolithography is in order.